1. Field of the Invention
The invention relates to a delay lock loop (DLL) circuit. Particularly, the invention relates to a delay lock loop circuit capable of generating a locked signal with 50% duty cycle.
2. Description of Related Art
According to a conventional technique, a delay lock loop (DLL) circuit is used for a synchronous semiconductor memory device in order to synchronize an internal clock signal with an external clock signal. In the synchronous semiconductor memory, data accessing operations such as a read operation and a write operating are performed in synchronous with rising edges and falling edges of the external clock signal. Since there is a time delay while the external clock signal is inputted to the synchronous semiconductor memory, such as the DLL is employed for synchronizing an internal clock signal with the external clock signal by compensating the time delay between the internal clock signal and the external clock signal.
However, in case of a double data rate (DDR) synchronous semiconductor memory device, the data accessing operations are performed at both of the rising edges and the falling edges of the internal clock signal. Therefore, it is required that the internal clock signal have a 50% duty cycle.